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| Distribution | Hardware-Verilog-Parser [Download] |
| Author | GSLONDON [ Greg London ] |
| Version | 0.13 |
| Abstract | A complete grammar for parsing Verilog code using perl |
| Released | 27 Apr 2000 |
| Size | 23.3 KB |
| MD5 Checksum | 13e484832847e133675160862b43d933 |
| Additional Files | README | Changes | Makefile.PL | |
| Links | search.cpan.org | CPAN::Forum | AnnoCPAN | rt.cpan.org | Rating | CPANTS | CPAN testers | Dependencies | Testers matrix |
| Hardware::Verilog::Hierarchy [source] [v 0.03] | |
| Hardware::Verilog::Parser [source] [v 0.13] | A complete grammar for parsing Verilog code using perl |
| Hardware::Verilog::StdLogic [source] [v 0.03] |
| trouchelle.com Perl 5.8 repository [ v 0.13 ] |
| Problems, suggestions, or comments to Randy Kobes. | Questions? Check the FAQ. | |
| Enable installations using PAR::WebStart. |