| Verilog-Perl documentation | Contained in the Verilog-Perl distribution. |
Verilog::Netlist::Defparam - Defparam assignment
use Verilog::Netlist;
...
foreach my $cont ($module->statements)
print $cont->name;
A Verilog::Netlist::Defparam object is created by Verilog::Netlist for every defparam in the current module.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Keyword used to declare the assignment. Currently "defparam" is the only supported value.
Left hand side of the assignment.
Pointer to the module the cell is in.
Reference to the Verilog::Netlist the cell is under.
Right hand side of the assignment.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Prints debugging information for this cell.
Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.
Copyright 2000-2011 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Wilson Snyder <wsnyder@wsnyder.org>
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
| Verilog-Perl documentation | Contained in the Verilog-Perl distribution. |
# Verilog - Verilog Perl Interface # See copyright, etc in below POD section. ###################################################################### package Verilog::Netlist::Defparam; use Verilog::Netlist; use Verilog::Netlist::Subclass; use vars qw($VERSION @ISA); use strict; @ISA = qw(Verilog::Netlist::Defparam::Struct Verilog::Netlist::Subclass); $VERSION = '3.307'; structs('new', 'Verilog::Netlist::Defparam::Struct' =>[name => '$', #' # Unique ID keyword => '$', #' # Keyword name filename => '$', #' # Filename this came from lineno => '$', #' # Linenumber this came from userdata => '%', # User information attributes => '%', #' # Misc attributes for systemperl or other processors # lhs => '$', #' # Left hand side of assignment rhs => '$', #' # Right hand side of assignment module => '$', #' # Module reference ]); sub delete { my $self = shift; my $h = $self->module->_statements; delete $h->{$self->name}; return undef; } ###################################################################### #### Methods sub logger { my $self = shift; return $self->netlist->logger; } sub netlist { my $self = shift; return $self->module->netlist; } sub lint {} sub link {} sub verilog_text { my $self = shift; my @out = ($self->keyword," ",$self->lhs," = ",$self->rhs,";"); return (wantarray ? @out : join('',@out)); } sub dump { my $self = shift; my $indent = shift||0; print " "x$indent,"Defparam:",$self->keyword," lhs:",$self->lhs," rhs:",$self->rhs; print "\n"; } ###################################################################### #### Package return 1; __END__