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Distribution Verilog-Perl [Download]
Author WSNYDER [ Wilson Snyder ]
Version 3.307
Abstract Verilog language utilities and parsing
Released 22 June 2011
Size 514.9 KB
MD5 Checksum f2a7b64f0bdf7b846770ff60e0d3a870
Additional Files README   |   META   |   Changes   |   Makefile.PL   |  
Links search.cpan.org   |   CPAN::Forum  |   AnnoCPAN  |   rt.cpan.org  |   Rating  | CPANTS  | CPAN testers | Dependencies | Testers matrix
Prerequisites Data::Dumper  |   Pod::Usage  |  

Modules

Verilog::EditFiles  [source]   [v 3.307] Split Verilog modules into separate files.
Verilog::Getopt  [source]   [v 3.307] Get Verilog command line options
Verilog::Language  [source]   [v 3.307] Language support, number parsing, etc
Verilog::Netlist  [source]   [v 3.307] Verilog Netlist
Verilog::Netlist::Cell  [source]   [v 3.307] Instantiated cell within a Verilog Netlist
Verilog::Netlist::ContAssign  [source]   [v 3.307] ContAssign assignment
Verilog::Netlist::Defparam  [source]   [v 3.307] Defparam assignment
Verilog::Netlist::File  [source]   [v 3.307] File containing Verilog code
Verilog::Netlist::Interface  [source]   [v 3.307] Interface within a Verilog Netlist
Verilog::Netlist::Logger  [source]   [v 3.035] Error collection and reporting
Verilog::Netlist::ModPort  [source]   [v 3.307] ModPort within a Verilog Interface
Verilog::Netlist::Module  [source]   [v 3.307] Module within a Verilog Netlist
Verilog::Netlist::Net  [source]   [v 3.307] Net for a Verilog Module
Verilog::Netlist::Pin  [source]   [v 3.307] Pin on a Verilog Cell
Verilog::Netlist::Port  [source]   [v 3.307] Port for a Verilog Module
Verilog::Netlist::Subclass  [source]   [v 3.307] Common routines for all classes
Verilog::Parser  [source]   [v 3.307] Language parsing
Verilog::Preproc  [source]   [v 3.307] Preprocess Verilog files
Verilog::SigParser  [source]   [v 3.307] Signal and module extraction
Verilog::Std  [source]   [v 3.307] SystemVerilog Built-in std Package Definition

Categories

Networking Devices IPC    >>     Verilog
Language Interfaces    >>     Verilog

Win32 PPM packages for "Verilog-Perl"

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